PhD in data compression for high-performance hardware acceleration circuits

Organisation/Company

Grenoble INP – Institute of Engineering

Department

Engineering

Research Field

Engineering » Electronic engineering

Researcher Profile

First Stage Researcher (R1)

Country

France

Application Deadline

5 Feb 2024 – 20:00 (Europe/Paris)

Type of Contract

Temporary

Job Status

Full-time

Offer Starting Date

1 Mar 2024

Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme

Reference Number

2023-DOCTCOMPRHP-TIMA

Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

The TIMA Laboratory is an academic research laboratory located in Grenoble city, in France. Research topics cover specification, design, verification, test, design tools (CAD) and design methods for embedded systems, from analog and digital components up to multicore system en chips (SoC), and their operating systems. The SLS team (System Level Synthesis) is focused on high-performance architectures for general-purpose computing and for more specific IA algorithms, and on system-level models and design methodologies : specification, simulation and verification of hardware/software systems on chips, design space exploration and synthesis of hardware.

Job description : Neural networks usually consist in performing a large number of matrix-vector and matrix-matrix multiplications. The design of hardware acceleration circuits for neural networks is thus mainly directed towards acceleration of these matrix operations. Considered matrices are often of great size, each with millions or tens of millions of parameters. The size of the memories of parameters and the actual throughput that is available for the computing units are design parameters of paramount importance. It has already been proposed to compress the parameters in memory in order to reduce the needs both in terms of size and of throughput. This generally takes advantage of the proportion of null parameters (the sparsity) within the contents of the matrices of parameters.

The drawback is that decompression operations have to be performed on the streams of data that feed the computing cores. And the compression methods that present a high compression ratio involve highly sequential operations and a complex control flow. The performance of the overall accelerator circuit are then limited by the speed at which the streams of data can effectively be decompressed. Other directions have been studied, with primary objective to maintain data throughput at high levels, but at the price of lower compression rations.

Previous works have studied compression of ternary values, but other types of compression are considered. Moreover, neural networks are inherently resilient against moderate computing errors. This property could be exploited to design compression types with better compression ratios. The objective of the PhD is to design low-complexity compression/decompression techniques that brings the least impact on performance of data transfers.

The following properties and freedom degrees will be taken into account in the design of efficient compression techniques :

• the nature of quantization and distribution of effectively used values,

• the structure of the execution units, • the order and distribution of values in memory,

• the impact on overall quality of results. The considered compression types may be lossless or lossy.

The impact on overall quality of results will be studied and potential mitigation techniques will be proposed. The cases of reconfigurable hardware targets (FPGA) and dedicated circuits (ASIC) will be considered.

Requirements

Research Field

Engineering » Electronic engineering

Education Level

Master Degree or equivalent

Skills/Qualifications

Requirements :

• Experience with AI flows and with architectures of neural networks

• Experience with digital signal processing, encoding of information and data compression

• Good programming skills, languages C / C++ / Python • Knowledge in architectures of digital circuits

• Knowledge in RTL languages would be a plus (Verilog or VHDL) Proficiency with English language is highly recommended. Proficiency with French language would be a plus. Interest in technologies of microelectronics and problem solving would be appreciated.

Specific Requirements

Specifics of the position The position will take place within offices of the TIMA Laboratory, in Grenoble city.

Position assigned to a restricted area:  (Device for the protection of the scientific and technical potential of the nation, conditioning the appointment of the researcher to the authorization of the Defense Security Officer).
 

Languages

ENGLISH

Level

Excellent

Languages

FRENCH

Level

Good

Internal Application form(s) needed
PHD DATA COMPRESSION FOR HIGH PERFORMANCE.pdf
English
(187.79 KB – PDF)
Download
Additional Information
Selection process

Applications must be sent to : [email protected]

Application deadline : 05/02/2024

Work Location(s)

Number of offers available

1

Company/Institute

TIMA

Country

France

Geofield

Where to apply

E-mail

[email protected]

Contact

City

Grenoble

Website

https://tima.univ-grenoble-alpes.fr/

Street

46 avenue Félix Viallet

Postal Code

38000

E-Mail

[email protected]

STATUS: EXPIRED