Senior Manager, R&D Hardware Engineering

Ciena

Job title:

Senior Manager, R&D Hardware Engineering

Company

Ciena

Job description

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.This position is for a Manager to lead the PCB HW design engineering team that delivers the hardware for the Packet Optical Platforms Group of products which may include Waveserver, WaveRouter & 6500 products.Responsibilities of the role include:

  • Manage a team of circuit pack Hardware designers, responsible for execution of defined Hardware project plans (schedule, performance, budget).
  • Manage execution of development plan according to product roadmap, in collaboration with various Architecture, Software, PLC (Product Life Cycle) and PLM (Product Line Management) teams.
  • Manage the hardware design activity from early concept phase, through architecture, prototype board bring-up, system test, product-verification to ultimate release of the product to the field
  • Address sustaining needs for newly released products to address customer and/or manufacturing test problems, and work with customer response teams as needed to root-cause and debug field issues.
  • Develop resource estimates and timelines for program feasibility and costing. Maintain resource profile view for the team for longer-term planning and responding to shifting priorities.
  • Collaborate with Architecture, Software, FPGA/ASIC & Mechanical/Thermal teams to ensure cross-functional communication and alignment to requirements. Highlight, communicate, and mitigate project risks.
  • Work closely with Ciena Operations, Test Engineering and Manufacturing to ensure build plans are communicated, tracked and aligned with project timelines.
  • Interact with Operations, Supply Chain, Quality teams and 3rd party vendors to ensure design for testability and manufacturability are aligned and ensure product cost is achieved as per the product cost targets.
  • Organize and execute detailed design reviews (Architecture, Schematic, Layout) to ensure the release of high-quality hardware designs.
  • Define achievable and clear expectations, provide timely individual feedback, recognize accomplishments and recommends appropriate skills training to enhance career development.
  • Help employees manage their careers, career and performance conversations, regular feedback and one-on-one discussions, Mentoring junior and senior engineers.
  • Ensure team is following the team conventions, guidelines, best practices.
  • Lead recruiting efforts as required, both full-time and contract employees.

Duties include:

  • Team management
  • Balance resources against workload
  • Encourage strong teamworking
  • Clear roadblocks for engineers
  • Facilitate employee development
  • Project Management
  • Manage activities to HW Project Launch, HW Pilot, GA, and follow the Product Life Cycle process
  • Facilitate cross functional collaboration
  • Manage risk, build plans, budget
  • Work very closely with the supplier FAEs and sales representatives

Required Skills:

  • Excellent communication skills
  • Excellent leadership
  • Excellent interpersonal and team skills
  • Highly motivated
  • Very thorough, detail oriented
  • Strong project management skills
  • Detailed knowledge of high-speed design (56G/112G PAM4), Signal Integrity and Manufacturing Guidelines.
  • Data and Telecommunications experience (400GE/800GE, OTN, PCI-e, QSFP-DD800, OSFP).
  • Experience with high layer-count PCB’s (24 layers +) and high-speed/high-power chipsets.
  • Bachelors Degree in Electrical Engineering or equivalent.
  • 10+ years relevant hardware design experience
  • Management experience an asset.

The role requires creative thinking, understanding of technical features, knowledge of the hardware design process and efficient / robust execution in breaking down higher level requirements into design tasks for ultimately delivering Hardware on time to enable product releases.The work environment is dynamic and rewarding. It involves closely working with established and growing top-notch engineers with a proven track record of delivering multiple generations of product lines over the past years.Compensation and BenefitsThe annual pay range for this position is $129,700 – $253,100 CAD.Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.Not ready to apply? Join our to get relevant job alerts straight to your inbox.At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.Ciena is an Equal Opportunity Employer, including disability and protected veteran status.If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Expected salary

Location

Ottawa, ON

Job date

Fri, 20 Dec 2024 06:46:04 GMT

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